1. Field of the Invention
The present invention generally relates to an apparatus for digital-to-analog conversion, and more particularly relates to an oversampling modulation apparatus of high-order topology.
2. Description of the Related Art
FIG. 1 illustrates a signal conversion processing of an oversampling modulation apparatus. The oversampling modulation apparatus 1 is applied to a digital-to-analog converter (DAC) for converting a pulse code modulation (PCM) signal 2 into a pulse density modulation (PDM) signal 3. PDM signal 3 is then converted into an analog signal through a filter (not shown). In FIG. 2, a Kth-order loop topology of an oversampling modulation apparatus is proposed by Chao et al.: A Higher Order Topology for Interpolative Modulators for Oversampling A/D Converters, published in IEEE Trans. Circuits and Sys., vol. CAS-37, pp. 309-318, Mar. 1990, wherein A1,A2, . . . , AK are feed forward loop coefficients and B1,B2, . . . , BK are feedback loop coefficients. The specific designated feedforward loop and feedback loop coefficients achieve specific modulating characteristics. FIG. 2 is expressed in Z-domain, while each of blocks 4, (Z.sup.-1 /1-Z.sup.-1), represents an integration circuit. Each of the state variables, SV1,SV2, . . . , SVK, is relative to the output value of a corresponding block 4. State variables, SV1,SV2, . . . , SVK, multiplied by their corresponding feedforward loop coefficients A1,A2, . . . , AK, through corresponding multipliers 6, are accumulated at an adder 7. Simultaneously, the output value of adder 7 is processed by a 1-bit quantizer 8 to form an output signal Y(Z), and is fed back to an adder 9 to be added with the output value of an adder 7' and the sampled signal X(Z). Specifically, output value of adder 7' comes from the accumulated value of the state variables, SV1,SV2, . . . , SVK, multiplied by the corresponding feedback loop coefficients, B1,B2, . . . , BK, through corresponding multipliers 5.
In the prior art, several efforts were made to achieve a two-order oversampling modulation apparatus (e.g., Candy et al., "Double Interpolation for Digital-to-Analog Conversion,"IEEE Trans. Commun., vol. COM-34, pp. 477-481, January 1986). Using conventional techniques it is difficult to provide for higher-order topologies because of the layout complexity which higher-order entails.